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For detailed information on the SH machine instruction set, see SH-Microcomputer Users Manual (Renesas) or SH-4 32-bit CPU Core Architecture (SuperH) and SuperH (SH) 64-Bit RISC Series (SuperH).
as
implements all the standard SH opcodes. No additional pseudo-instructions are needed on this family. Note, however, that because as
supports a simpler form of PC-relative addressing, you may simply write (for example)
mov.l bar,r0
where other assemblers might require an explicit displacement to bar
from the program counter:
mov.l @(disp, PC)