NXP LPC4300 CPU Support Package

This package contains project templates and system files for the NXP LPC4300.

CrossWorks Version 3 Installation Instructions

To install this support package

1. Click the Tools > Package Manager menu option to open the package manager window.
2. Right click on the NXP LPC4300 CPU Support Package entry and select Install Selected Packages.
3. Click Next to take you to the summary page.
4. Click Next to install the package.
5. Click Finish to close the package manager window.
6. Click the Tools > Show Installed Packages.
7. Click on the NXP LPC4300 CPU Support Package link to view the package and its contents.

To manually install this support package

1. If you have not done so already, follow the CMSIS 3 Support Package and CrossWorks Tasking Library Package installation instructions.
2. Download the file LPC4300.hzq using your web browser.
3. Click the Tools > Manually Install Packages menu option.
4. Select the file you have just downloaded to install the package.
5. Click the Tools > Show Installed Packages.
6. Click on the NXP LPC4300 CPU Support Package link to view the package and its contents.

To install this support package using other versions

• CrossWorks Version 2 Installation Instructions

Release Notes

1.7

• Added more dual core samples.
• Added ctl_sleep/ctl_woken/ctl_lowest_isr_priority/ctl_highest_isr_priority/ctl_adjust_isr_priority to LPC4300_ctl.c.
• Fixed __NVIC_PRIO_BITS in LPC43xx.h.
• Cortex-M0 projects now have their own memory maps.
• Added test10.c to ctl tests.
• Rearranged System Control Space register groups in registers window.
• Added flash loader support for writing eeprom memory.

1.6

• Added support for LPC4370.
• Added SDRAM placement capability.

1.5

• Changed ID2 identify test to only check the lower 16 bits.

1.4

• New CTL projects now allocate a process stack. If you have an existing CTL project then you should do similar since this is required for the CTL supplied with CrossWorks for ARM version 2.3.1.

1.3

• Fixed IdentifyPart() script.
• Fixed Dual Core project file.

1.2

• Improved support for Cortex-M0 projects. Existing Cortex-M0 projects should be recreated using one of the Cortex-M0 project templates.
• Added support for LPC4353 and LPC4357 devices.
• Removed from the startup code the disabling of the Cortex-M4F hardware lazy FP save feature for CTL. CTL supplied in CrossWorks for ARM version 2.3 supports the Cortex-M4F hardware lazy FP save feature.
• Removed core CMSIS header files from this package. New projects will reference the include directory $(TargetsDir)/CMSIS_3/CMSIS/Include of the CMSIS-3 package. If you have an existing project then you will have to add $(TargetsDir)/CMSIS_3/CMSIS/Include to the User Include Directories project property.
• Renamed IRQHandler function names in the startup code to match the latest user guide names:
  • M0a_IRQHandler renamed to be M0CORE_IRQHandler.
  • ETH_IRQHandler renamed to be ETHERNET_IRQHandler.
  • RIT_IRQHandler renamed to be RITIMER_IRQHandler.
  • UART0_IRQHandler renamed to be USART0_IRQHandler - same for 2 and 3.
  • GPIO0_IRQHandler renamed to be PIN_INT0_IRQHandler - same for 1, 2, 3, 4, 5, 6 and 7.
  • EVRT_IRQHandler renamed to be EVENTROUTER_IRQHandler.
  • CAN1_IRQHandler renamed to be C_CAN1_IRQHandler.
  • WDT_IRQHandler renamed to be WWDT_IRQHandler.
  • CAN0_IRQHandler renamed to be C_CAN0_IRQHandler.
• The target script now identifies the device based on connect and enables the ETB.
• Provided sample project file for CMSIS-3 DSP Lib samples.

1.1

• Removed RESERVED bitfields from memory maps.

1.0

• Initial Release.

Documentation

Creating LPC4300 Projects

To create a new LPC4300 project

• Select the File > New > New Project menu item.
• Select the required Generic LPC4300 from the Project Type list.
• Select the LPC4300 Executable project template type from the Templates list.
• Set the required project name and location directory.
• Click OK .

To build, load and debug an application running in internal RAM

• Select the project to work on by using the Project | Set Active Project menu option.
• Select the RAM placement by clicking on the project node in the project explorer.
• Build the project by using the Build | Build Project menu option.
• Connect to the appropriate target in the target window.
• Download and start debugging the current project by using Debug | Start Debugging .

To build, load and debug an application running in internal Flash.

• Select the project to work on by using the Project | Set Active Project menu option.
• Select the Flash A placement by clicking on the project node in the project explorer.
• Build the project by using the Build | Build Project menu option.
• Connect to the appropriate target in the target window.
• Download and start debugging the current project by using Debug | Start Debugging .

To make the application startup from reset

• Right click on the project node in the project explorer and select Properties...
• In the properties window scroll down to the Preprocessor Options section.
• Type STARTUP_FROM_RESET into the Preprocessor Definitions property editor.

LPC4300 Project Specifics

CMSIS support

CMSIS header files are included as part of the new project setup.

• LPC43xx.h LPC43xx specific header file.

CTL support

The file LPC4300_ctl.c implements the CTL system timer using the Cortex-M4 SysTick timer or for the Cortex-M0 the RTI timer. The timer is configured to interrupt at a 10 millisecond rate and increment the CTL system timer by 10 to give a millisecond timer. The implementation uses the CMSIS SystemFrequency global variable to determine the CPU clock frequency.

Memory Simulator

An memory simulator is provided that simulates the memories of the various LPC4300 devices. The memory simulation parameter specifies the device name and the sizes of the SPIFI and the 4 static memories as macro values that can be defined with the memory simulation parameter macros project property.

Project Templates

The following project templates are supplied.

• LPC4300 Executable - a program that runs on the Cortex-M4 of the LPC4300.
• LPC4300 Externally Built Executable - a project to load and debug a program on the Cortex-M4 of the LPC4300.
• LPC4300 CTL Executable - a CrossWorks Tasking Library project that runs on the Cortex-M4 of the LPC4300.
• LPC4300 Cortex-M0 Executable - a program that runs on the Cortex-M0 of the LPC4300.
• LPC4300 Cortex-M0 Externally Built Executable - a project to load and debug a program on the Cortex-M0 of the LPC4300.
• LPC4300 Cortex-M0 CTL Executable - a CrossWorks Tasking Library project that runs on the Cortex-M0 of the LPC4300.
• LPC4370 Cortex-M0 SUBSYSTEM Executable - a project that runs on the Cortex-M0 SUBSYSTEM of the LPC4370.

Section Placement

CrossStudio for ARM supports LPC4300 projects running applications in a number of different memory configurations. You can select the memory configuration you require by right clicking on the project node in the project explorer and selecting the Placement entry.

For LPC4300 projects the set of placements are:

• EMC application runs in external memory.
• EMC Copy To RAM application boots from external memory into local SRAM.
• Flash A application runs in internal flash memory bank A.
• Flash A Copy to RAM application boots from internal flash memory bank A into local SRAM.
• Flash B application runs in internal flash memory bank B.
• Flash B Copy to RAM application boots from internal flash memory bank B into local SRAM.
• RAM application runs in local SRAM.
• SDRAM application runs in external SDRAM.
• SPIFI application runs in SPIFI memory.
• SPFI Copy To RAM application boots from SPIFI memory into local SRAM.

Stack and Heap Sizes

The stack and heap sizes are set to be 256 bytes by default when a project is created. It is likely that you will need to change these values.

Target Reset Script

The reset script LPC4300_Target.js is used by the debugger to reset the target board.

Target Startup Code

The startup code LPC4300_Startup.s and LPC4300_CM0_Startup.s are common to all LPC4300 processors. There are a set of preprocessor defines that configure the startup code and are documented in the startup file itself. The startup code calls out to a weak symbol SystemInit with the stack pointer set to the top of RAM. The SystemInit function can be used to set the CPU clock or configure any external memories prior to the C initialisation code and as such it cannot access initialised static data.

The startup code LPC4300_CM0SUB_Startup.s is specific to the Cortex-M0 SUBSYSTEM of the LPC4370.

Board Specific Files

The board specific file LPC4300_ctl_board.c is included in the samples that implements SystemInit() and the ctl board support functions to flash a led and handle a button press.

Running Dual Core Samples

Note that dual core debug is currently only supported with Rowley implemented target interfaces i.e. CrossConnect, CMSIS-DAP, FTDI2232 and Wiggler.

• Select the _CM4 project as the active project and build it.
• The _CM0 project will be built since it is a dependent project.
• Connect to the target and start debugging. This will load the _CM4 project and then load the _CM0 project since the "Debug Dependent Projects" is set to "Yes".
• The debugger will stop in the _CM4 project.
• You can now debug the _CM4 project.
• You can select the _CM0 project using the toolbar in the text editor window.
• The debugger will stop in the _CM0 project.
• You can now debug the _CM0 project.
• At any time you can switch projects noting that the debug state of the project is not changed by the project switch.