NXP Vybrid CPU Support Package
This package contains project templates and system files for the NXP Vybrid.
CrossWorks Version 4 Installation Instructions
This package can only be installed if you have the following CrossWorks license bolt-ons:
- ARM License
- To install this support package
-
- Click the Tools > Package Manager menu option to open the package manager window.
- Right click on the NXP Vybrid CPU Support Package entry and select Install Selected Packages.
- Click Next to take you to the summary page.
- Click Next to install the package.
- Click Finish to close the package manager window.
- Click the Tools > Show Installed Packages.
- Click on the NXP Vybrid CPU Support Package link to view the package and its contents.
- To manually install this support package
-
- If you have not done so already, follow the CMSIS 3 Support Package and CrossWorks Tasking Library Package installation instructions.
- Download the file Vybrid.hzq using your web browser.
- Click the Tools > Manually Install Packages menu option.
- Select the file you have just downloaded to install the package.
- Click the Tools > Show Installed Packages.
- Click on the NXP Vybrid CPU Support Package link to view the package and its contents.
- To install this support package using other versions
Release Notes
1.5
- Add reset script support for 2N device.
- Fixed connect issues with Vybrid_Target.js when using CrossWorks V4.3.0 and above.
- Changed Vybrid_Startup.s to be assemblable with clang.
1.4
- Fixed missing CMSIS_3 dependency.
1.3
- Modified ResetCM4() in Vybrid_Target.js to reset the core and then disable the caches.
- Added MCM and LMEM register group to the CM4 registers window.
- Enabled CLOCK_SETUP 1 in system_Vybrid.c.
1.2
- Fixed CTL tasking on Cortex-M4.
- Added ctl_lowest_isr_priority/ctl_highest_isr_priority/ctl_adjust_isr_priority to Vybrid_ctl.c.
- Fixed errors/warnings when building with soft floating point.
- Fixed NESTED_INTERRUPT support in irq_handler.
1.1
- Modified reset script so that reconnect isn't required after each debug session.
- Added support for j-link - note that dual core debug is not supported with j-link.
1.0
- Initial Release.
Documentation
Creating Vybrid Projects
To create a new Vybrid project
- Select the File > New > New Project menu item.
- Select the appropriate Generic Vybrid from the Categories list.
- Select the required project template type from the Templates list.
- Set the required project name and location directory.
- Click OK.
To build and debug an application the runs in OCRAM
- Select the project to work on by using the Project > Set Active Project menu option.
- Select the OCRAM placement by clicking on the project node in the project explorer.
- Build the project by using the Build | Build Project menu option.
- Connect to the appropriate target in the target window.
- Download and start debugging the current project by using Debug > Start Debugging.
Vybrid Project Specifics
Target Processor
Once a project has been created you can select different target processors from the selected set by right clicking on the project node in the project explorer and selecting the Target property.
Selecting the target processor will specify the memory map that is used for the build and debug. You can view the selected memory map by right clicking on the project node in the project explorer and selecting Edit Memory Map. In the memory map files the memory segments defining the names, sizes and access types of the external memories are specified using macros which can be set using the Memory Map Macros project property.
Section Placement
CrossStudio for ARM supports Vybrid projects running applications in a number of different memory configurations. You can select the memory configuration you require by right clicking on the project node in the project explorer and selecting the Placement property.
For Vybrid Cortex-A5 projects the set of placements are:
- OCRAM application runs in internal SRAM.
- DDR application runs in external DDR.
- QuadSPI0 application runs in external QuadSPI.
For Vybrid Cortex-M4 projects the set of placements are:
- OCRAM application runs in internal SRAM.
- TCM application runs in internal TCM.
- DDR application runs in external DDR.
- QuadSPI0 application runs in external QuadSPI.
To make use of the Cortex-M4 PC bus you can modify (a project local copy of) the section placement file to specify a runoffset. For example for an OCRAM build you can run the text in the OCRAM code alias space by adding runoffset="-0x20000000" to the text section.
Target Startup Code
In the startup code for the CA5 Vybrid_Startup.s there are a set of preprocessor defines that configure the startup code and are documented in the startup file itself.
In the startup code for the CM4 Vybrid_Startup2.s there are a set of preprocessor defines that configure the startup code and are documented in the startup file itself.
Target Reset Script
The reset script Vybrid_Target.js resets the target using the MDM AP and stops it in the bootloader. You should always ensure that the board enters the bootloader after reset.
Memory Simulator
An Vybrid memory simulator is provided that simulates the memories of the various Vybrid devices. The memory simulation parameter (which is set by the Target Processor selection) contains macros that determine the sizes of the simulated memories and can be specified using the Memory Simulation Parameter Macros property.
CTL support
The file Vybrid_ctl.c implements the ctl_set_isr, ctl_unmask_isr and ctl_mask_isr functions by programming the GIC/NVIC/MSCM_IRC register groups. The vector parameter to these functions corresponds to the GIC interruptID as defined in the Vybrid reference manual. The same vector numbers can be used for both CA5 and CM4 interrupt handlers e.g. the CM4 vector 32 corresponds to the CPU to CPU int0 vector for both cores. For the CA5 the priority parameter to the ctl_set_isr is the GIC priority i.e. lower numbers have higher priorities. For the CA5 if nested interrupts are enabled for the irq_handler then the priority is a pre-emption priority i.e. interrupt handlers can be interrupted by higher priority interrupt handlers. For the CM4 the priority has 8 added to it so that it is always in the lowest half of the priority range. The startup code Vybrid_Startup.s implements the CA5 irq_handler exception handler.
Header and Library Files
The NXP header and system init files are provided.